24. CPLD И FPGA

 
  THIS SECTION IS UNDER CONSTRUCTION  
 


  


Flexware

  


PLD	Programming logic devices

  


SPLD	Simple PLD (both PLA and PAL)



  
  PLA 
 

PLA	Programming logic array
	small FPD contain 2 level of logic AND and OR plane,
	both planes is programmable

  

  




  
  PAL 
 

PAL	Programmable array logic
	small FPD contain programmable AND plane, fixed OR plane

  


Logic expander:
  


	PAL GAL
	CUPL

Lattice PAL16L8:
  


Как мы видим контакты:
	10		GND
	1-9,11		in
	13-18		in/out
	12,19		out
	20		VCC

Пример программы на PALASM для дешифратора:
-----------------------------------------------------------------------

TITLE	 Address Decoder
PATTERN	 Test 1
REVISION A
AUTOR	 AVP
COMPANY	 PHG
DATA	 26/2/06
CHIP	 DECODER1 PAL16L8
; pins 1   2   3   4   5    6  7   8    9   10
       A10 A11 A12 A13 A14 A15 A16 A17	A18 GND
; pins 11  12 13  14  15  16  17   18  19  20
       A19 NC A20 A21 A22 A23 A24  NC  CS  VCC 

EQUATIONS

/CS = A24 * A23 * A22 * A21 * A20 * A19 * A18 * A17 * A16
    + A24 * A23 * A22 * A21 * /A11 * /A10

-----------------------------------------------------------------------



  
  CPLD 
 

CPLD	Complex PLD 
	multiple SPLD blocks in single chip

  


  




  
  FPGA 
 

FPGA	Field Programmable Grid Array
	Structure allow very high logic capacity

  


  


  


  


	Lookup table
	CLB (configurable logic block)

  


  






FPGA


характеристики современных FPGA


Когда делают новый техпроцесс первым делом на нем выпускают не процессоры
а FPGA.

Military Xilinx Vertex-4E стоит $20,000 за chip.

	------------------------------
	тип	Экивалентных вентилей
	------------------------------
	SPLD	0-200
	CPLD	200-12000
	FPGA	1000-1000000
	------------------------------
	


Xilinx	Virtex		Full-feature SRAM-based FPGA
	Spartan		Low-cost reduced version
	CoolRunner	CPLD
Altera	Stratix		SRAM based FPGA
	Cyclone		Low-cost reduced version
	MAX		CPLD
	MAX-II		Flash based CPLD
Actel			Antifuse based FPGA (radiation tolerant)
			Flash based FPGA
Lattice			CPLD (EEPROM)
			Flash based FPGA

  


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