56.8.




THIS SECTION IS UNDER CONSTRUCTION











LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY baudcontroller IS PORT( clk : IN std_logic; rst : IN std_logic; baud : IN std_logic_vector(0 to 2); clkout : OUT std_logic); END baudcontroller; ARCHITECTURE simple OF baudcontroller IS SIGNAL clkdiv : integer := 0; SIGNAL count : integer := 0; BEGIN Div: process (rst, clk) begin if rst = '0' then clkdiv <= 0; count <= 0; elsif rising_edge(CLK) then case Baud is when "000" => clkdiv <= 7; -- 115200 when "001" => clkdiv <= 15; -- 57600 when "010" => clkdiv <= 23; -- 38400 when "011" => clkdiv <= 47; -- 19200 when "100" => clkdiv <= 95; -- 9600 when "101" => clkdiv <= 191; -- 4800 when "110" => clkdiv <= 383; -- 2400 when "111" => clkdiv <= 767; -- 1200 when others => clkdiv <= 7; end case; end if; end process; clockdivision: process (clk, rst) begin if rst='0' then clkdiv <= 0; count <= 0; elsif rising_edge(CLK) then count <= count + 1; if (count > clkdiv) then clkout <= not clkout; count <= 0; end if; end if; end process; END simple; ENTITY serialrx IS PORT( clk : IN std_logic; rst : IN std_logic; rx : IN std_logic; dout : OUT std_logic_vector (7 downto 0) ); END serialrx; ARCHITECTURE simple OF serialrx IS type state is (idle, s0, s1, s2, s3, s4, s5, s6, s7, stop); signal current_state, next_state : state; signal databuffer : std_logic_vector(7 downto 0); BEGIN receive: process (rst, clk) begin if rst='0' then current_state <= idle; for i in 7 downto 0 loop dout(i) <= '0'; end loop; elsif rising_edge(CLK) then case current_state is when idle => if rx = '0' then next_state <= s0; else next_state <= idle; end if; when s0 => next_state <= s1; databuffer(0) <= rx; when s1 => next_state <= s2; databuffer(1) <= rx; when s2 => next_state <= s3; databuffer(2) <= rx; when s3 => next_state <= s4; databuffer(3) <= rx; when s4 => next_state <= s5; databuffer(4) <= rx; when s5 => next_state <= s6; databuffer(5) <= rx; when s6 => next_state <= s7; databuffer(6) <= rx; when s7 => next_state <= stop; databuffer(7) <= rx; when stop => if rx = '0' then next_state <= s0; else next_state <= idle; end if; dout <= databuffer; end case; current_state <= next_state; end if; end process; END;


Flow control:






PnP




Modem cable






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