4.3.4. ТРАНЗИСТОР ПОЛЕВОЙ (JFET)

JFET - Junction Field Electric Transistor
Полевой транзистор - управляется электрическим полем

Полевой транзистор - трехэлектродный полупроводниковый прибор, в котором
управление током осуществляется путем изменения проводимости токопроводящего 
канала, путем воздействия электрического поля перпендикулярного направлению тока.


JFET состоит из узкой области одного типа проводимости, окруженной
областью другово типа проводимости.
В этой узкой области путем приложения напряжение к более большой области
формируется поле, мешающее передвижению зарядов.
  


Таким образом в отличии от BJT JFET управляется полем

  




VHDL-AMS модель N-JFET:

	PACKAGE electricalSystem IS
    		NATURE electrical IS real ACROSS real THROUGH;
    		FUNCTION POW(X,Y: real) RETURN real;
    		FUNCTION SIN(X : real) RETURN real;
    		FUNCTION EXP(X : real) RETURN real;
    		FUNCTION SQRT(X : real) RETURN real;
	END PACKAGE electricalSystem;

	use work.electricalsystem.all;

	entity njfet is
    		generic(T : real := 300.0;
	    		vto : real := -2.0;    -- Zero-bais threshold voltage
	    		beta : real := 1.0e-4; -- transconductance parameter
	    		lambda : real := 0.0;  -- channel lenght modulation
	    		af : real := 1.0;      -- flicker noise exponent
	    		kf : real := 0.0;      -- flicker noise coefficient
	    		iss : real := 1.0e-14; -- gate junction saturation current
	    		pb : real := 1.0;      -- gate junction potential
	    		fc : real := 0.5;      -- forward-bais depletion capacitance coeff
	    		cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
	    		cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
	    		rd : real := 1.0e-6;   -- drain ohmic resistance
	    		rs : real := 1.0e-6);  -- source ohmic resistance
    		port (terminal g,s,d : electrical);
	end entity njfet;

	architecture behav of njfet is
  		terminal d1, s1 : electrical;
  		quantity vds across id through d1 to s1;
  		quantity vrd across ird through d to d1;
  		quantity vrs across irs through s1 to s;
  		quantity vgs across igs through g to s1;
  		quantity vgd across igd through g to d1;
  		constant gmin : real := 1.0e-12;
  		quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
  		quantity vds_free : real := 2.0;
  		quantity vgs_free : real := 0.0;
  		quantity vgd_free : real := 2.0;
	begin
  		------ Setting initial conditions
  		initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0;
  		therm_volt : ktq == 2.586e-2 * (T/300.0);
  		dres : vrd == ird * rd;
  		oup_res : vds_free == vds;
  		inp_res : vgs_free == vgs;
  		vgdf : vgd_free == vgd;
  		sres : vrs == irs * rs;

	---- Current is in Amps.
	-- Normal mode
		  ------ Cut off Region
      regions : if((vgs <= vto) and (vds >= 0.0))use
			gncn : id == 1.0e-9 * vds;
  		------ Linear Region
  		elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use
      			gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free);
  		------ Saturation Region
  		elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use
     			gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free);
	-- Inversted mode
  		------ Cut off Region
  		elsif((vgd <= vto) and (vds < 0.0))use
			gnci : id == 1.0e-9 * vds;
  		------ Linear Region
  		elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use
      			gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free);
  		------ Saturation Region
  		elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use
     			gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free);
  		end use;

	----- Gate diode equations 
  		initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0;
  
   		----- Gate to source
   		subcond1 : if(vgs > -5.0*ktq) use
			gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs));
   		elsif(vgs <= -5.0*ktq ) use
   			gsr : igs == -1.0*iss + (gmin*vgs);
   		end use;
   		----- Gate to drain
   		subcond2 : if(vgd > -5.0*ktq) use
			gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd));
   		elsif(vgd <= -5.0*ktq ) use
    			gdr : igd == -1.0*iss + (gmin*vgd);
   		end use;
	end architecture behav;



VHDL-AMS модель P-JFET:

	PACKAGE electricalSystem IS
    		NATURE electrical IS real ACROSS real THROUGH;
    		FUNCTION POW(X,Y: real) RETURN real;
    		FUNCTION SIN(X : real) RETURN real;
    		FUNCTION EXP(X : real) RETURN real;
    		FUNCTION SQRT(X : real) RETURN real;
	END PACKAGE electricalSystem;

	use work.electricalsystem.all;

	entity pjfet is
    		generic(T : real := 300.0;
	    		vto : real := -2.0;   -- Zero-bais threshold voltage
	    		beta : real := 1.0e-4; -- transconductance parameter
	    		lambda : real := 0.0;  -- channel lenght modulation
	    		af : real := 1.0;      -- flicker noise exponent
	    		kf : real := 0.0;      -- flicker noise coefficient
	    		iss : real := 1.0e-14; -- gate junction saturation current
	    		pb : real := 1.0;      -- gate junction potential
	    		fc : real := 0.5;      -- forward-bais depletion capacitance coeff
	    		cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
	    		cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
	    		rd : real := 1.0e-6;   -- drain ohmic resistance
	    		rs : real := 1.0e-6);  -- source ohmic resistance
   	 	port (terminal g,s,d : electrical);
	end entity pjfet;

	architecture behav of pjfet is
  		terminal d1, s1 : electrical;
  		quantity vds across id through s1 to d1;
  		quantity vrd across ird through d1 to d;
  		quantity vrs across irs through s to s1;
  		quantity vgs across igs through s1 to g;
  		quantity vgd across igd through d1 to g;
  		constant gmin : real := 1.0e-12;
  		quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
  		quantity vds_free : real := 2.0;
  		quantity vgs_free : real := 0.0;
  		quantity vgd_free : real := 2.0;
	begin
  		------ Setting initial conditions
  		initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0;
  		therm_volt : ktq == 2.586e-2 * (T/300.0);
  		dres : vrd == ird * rd;
  		oup_res : vds_free == vds;
  		inp_res : vgs_free == vgs;
  		vgdf : vgd_free == vgd;
  		sres : vrs == irs * rs;

		---- Current is in Amps.
      -- Normal mode
  		------ Cut off Region
      regions : if((vgs <= vto) and (vds >= 0.0))use
			gncn : id == 1.0e-9 * vds;
  		------ Linear Region
  		elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use
      			gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free);
  		------ Saturation Region
  		elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use
     			gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free);

    -- Inversted mode
  		------ Cut off Region
  		elsif((vgd <= vto) and (vds < 0.0))use
			gnci : id == 1.0e-9 * vds;
  		------ Linear Region
  		elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use
      			gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free);
  		------ Saturation Region
  		elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use
     			gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free);
  		end use;
  
   ----- Gate diode equations 
  		initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0;

   		----- Gate to source
 		subcond1 : if(vgs > -5.0*ktq) use
			gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs));
   		elsif(vgs <= -5.0*ktq ) use
   			gsr : igs == -1.0*iss + (gmin*vgs);
   		end use;
   		----- Gate to drain
   		subcond2 : if(vgd > -5.0*ktq) use
			gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd));
   		elsif(vgd <= -5.0*ktq ) use
    			gdr : igd == -1.0*iss + (gmin*vgd);
   		end use;
	end architecture behav;