11.1.




Def
===
	 -    
	  A  B    (S  P)  
	    .
	[ HA = Half Adder ]



------+------- A B | P S ------+------- 0 0 | 0 0 0 1 | 0 1 1 0 | 0 1 1 1 | 1 0 -------------- XOR:


library ieee; use ieee.std_logic_1164.all; entity HSUM1 is port( B1, B2 : in std_logic; C, S : out std_logic); end HSUM1; architecture Example of HSUM1 is begin S <= ((B1 and (not B2)) or ((not B1) and B2)); C <= B1 and B2; end Example;




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