19.




THIS SECTION IS UNDER CONSTRUCTION


:

VHDL: library ieee; use ieee.std_logic_1164.all; entity BIDIR is port( y : inout std_logic; e,a : in std_logic; b : out std_logic ); end BIDIR; architecture ARCH of BIDIR is begin process(e,a) begin case e is when '1' => y <= a; when '0' => y <= 'Z'; when others => y <= 'X'; end case; end process; b <= y; end ARCH;


( , ).



(a) - () - () - -


.




bus holder




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