35.2.1.3.





Shift Arithmetical Left

------------------------------------------------------------------------------ o Shift Arithetical Left x86 \ Alpha |--- alias to shift logical left on this architectures. PPC | MIPS /


Shift Arithmetical Right



	destination = source >>> count
------------------------------------------------------------------------------ o Shift Arithmetical Right x86 SAR 8 Rcl RI 16 Rcl RI 32 Rcl RI -------------------------------------- Alpha SRA 64 RRR RRI -------------------------------------- PPC SRAW max RRR SRAWI max RRI -------------------------------------- MIPS SRA 32 RRI SRAV 32 RRR DSRA 64 RRI DSRAV 64 RRR -------------------------------------- SPARC SRA max RRR RRI -------------------------------------- 68K ASR 8 RR RI (D-regs) 16 RR RI 32 RR RI --------------------------------------- z80 SRA 8 R --------------------------------------- MCS51 (*) Complex --------------------------------------- JVM ISHR 32 LSHR 64 --------------------------------------- ARM (*) MOV wih operand2 = r ASR r --------------------------------------- SH4 SHAR R (shift by 1 bit)


Shift Logical Left



	destination = source << count
------------------------------------------------------------------------------- o Shift Logical Left x86 SHL 8 Rcl RI 16 Rcl RI 32 Rcl RI -------------------------------------- Alpha SLL 64 RRR RRI -------------------------------------- PPC SLW max RRR -------------------------------------- MIPS SLL 32 RRI SLLV 32 RRR DSLL 64 RRI DSLLV 64 RRR -------------------------------------- SPARC SLL max RRR RRI -------------------------------------- 68K LSL 8 RR RI (D-regs) 16 RR RI 32 RR RI -------------------------------------- z80 SLA 8 R -------------------------------------- HPPA VEXTRUc 32 R,I5,R (Extract Unsigned) VEXTRSc 32 R,I5,R (Extract Signed) EXTRUc 32 R,R,I5,R (Extract Unsigned) EXTRSc 32 R,R,I5,R (Extract Signed) -------------------------------------- IA-64 SHL 64 R1=R2,R3 R1=R2,count(6) (Pop: dep.z r1=r2,count(6), 64-count(6). -------------------------------------- MCS51 (*) Complex sequence -------------------------------------- JVM ISHL 32 LSHL 64 --------------------------------------- ARM (*) MOV wih operand2 = r LSL r --------------------------------------- SH4 SHLL R (shift by 1 bit) SHLL2 R (shift by 2 bits) SHLL8 R (shift by 8 bits) SHLL16 R (shift by 16 bits)


Shift Logical Right



	destination = source >> count
------------------------------------------------------------------------------- o Shift Logical Right x86 SHR 8 Rcl RI 16 Rcl RI 32 Rcl RI -------------------------------------- Alpha SLR 64 RRR RRI -------------------------------------- PPC SRW max RRR -------------------------------------- MIPS SRL 32 RRI SRLV 32 RRR DSRL 64 RRI DSRLV 64 RRR -------------------------------------- SPARC SRL max RRR RRI -------------------------------------- 68K LSR 8 RR RI (D-regs) 16 RR RI 32 RR RI -------------------------------------- z80 SRL 8 R -------------------------------------- HPPA VSHDc 32 RRR (Variable Shift Double) SHDc 32 RR,i5,R -------------------------------------- IA-64 SHR 64 R1 = R3,R2 (Signed) R1 = R3, count(6) SHR.U 64 R1 = R3,R2 (Unsigned) R1 = R3, count(6) -------------------------------------- MCS51 (*) Complex Sequence --------------------------------------- JVM IUSHR 32 LUSHR 64 --------------------------------------- ARM (*) MOV wih operand2 = r LSR r --------------------------------------- SH4 SHLR R (shift by 1 bit) SHLR2 R (shift by 2 bits) SHLR8 R (shift by 8 bits) SHLR16 R (shift by 16 bits) ------------------------------------------------------------------------------


Rotates

Note: Rotates usually makes then RRR or RR registers are the same. IA-64 SHLADD R1=R2,count(2),R3 Shift Left + Add SHRP R1=R2,R3,count(6) Shift Right Pair Rotates: ARM: MOV with operand2 = r ROR x (Rotate Right) PPC: rotldi ra,rs,n rldicl ra,rs,n,0 rotrdi ra,rs,n rldicl ra,rs,64-n,0 rotld ra,rs,rb rldcl ra,rb,rb,0 sldi ra,rs,n rldicl ra,rs,n,63-n PowerPC srdi Rx,Ry,N => rldicl Rx,Ry,64-n,n srwi Rx,Ry,N => rlwinm Rx,Ry,32-n,n,31 clrrwi Rx,Ry,N => rlwinm Rx,Ry,0,0,31-n PowerPC: ( Shift Rotate Extract Bit).




Rotate Left



	destination = source ROL count
--------------------------------------------------------------------------- o Rotate Left x86 ROL 8 RR{CL} RI 16 RR{CL} RI 32 RR{CL} RI ------------------------------------ Alpha ------------------------------------ PPC RLWNM max RRRII Rotate Left and AND with MASK RLWNM. max RRRII ------------------------------------ MIPS ------------------------------------ SPARC ------------------------------------ HPPA ------------------------------------ 68K ROL 8 RR RI 16 RR RI 32 RR RI ------------------------------------ VAX-11 ------------------------------------ ARM ------------------------------------ IA-64 ------------------------------------ SH4


Rotate Right



	destination = source ROR count
--------------------------------------------------------------------------- o Rotate Right x86 ROR 8 RR{CL} RI 16 RR{CL} RI 32 RR{CL} RI ------------------------------------ Alpha ------------------------------------ PPC ------------------------------------ MIPS ------------------------------------ SPARC ------------------------------------ HPPA ------------------------------------ 68K ROR 8 RR RI 16 RR RI 32 RR RI ------------------------------------ VAX-11 ------------------------------------ ARM ------------------------------------ IA-64 ------------------------------------ SH4


Rotate through Carry Left



	destination = source RCL count
--------------------------------------------------------------------------- o Rotate throught Carry Left x86 RCL 8 RR{CL} RI 16 RR{CL} RI 32 RR{CL} RI ------------------------------------ Alpha ------------------------------------ PPC ------------------------------------ MIPS ------------------------------------ SPARC ------------------------------------ HPPA ------------------------------------ 68K ROXL 8 RR RI 16 RR RI 32 RR RI ------------------------------------ VAX-11 ------------------------------------ ARM ------------------------------------ IA-64 ------------------------------------ SH4


Rotate through Carry Right



	destination = source RCR count
--------------------------------------------------------------------------- o Rotate throught Carry Right x86 RCR 8 RR{CL} RI 16 RR{CL} RI 32 RR{CL} RI ------------------------------------ Alpha ------------------------------------ PPC ------------------------------------ MIPS ------------------------------------ SPARC ------------------------------------ HPPA ------------------------------------ 68K ROXR 8 RR RI 16 RR RI 32 RR RI ------------------------------------ VAX-11 ------------------------------------ ARM ------------------------------------ IA-64 ------------------------------------ SH4

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