35.2.1.4. РАБОТА С ПАМЯТЬЮ

Работа с памятью - загрузка частей


Alpha:	Load 32-bit unsigned
		LDL
		LDU  EXTLL



  
  Load 
 

  


	destination = Memory[EA](Size)

Пример когда размер памяти равен размера регистра



  


	destination = sign_extent(Memory[EA](Size))

Загрузка части с расширением знака.



  


	destination = zero_extent(Memory[EA](Size))



 ------------------------------------------------------------------------------
o	Load BYTE (8-bit)

	x86	MOV		R[Ar+Ir+Disp]
	-----------------------------------------
	Alpha	(*)	LDL/LDQ, then EXTBL  RRR RRI
	-----------------------------------------
	PPC	LBA	??
		LBAX	??
		LBZ		R[Ar]
		LBZX		R[Ar+Ir]
	------------------------------------------
	MIPS	LB		R[Ar+Disp]		
		LBU		R[Ar+Disp]
	------------------------------------------
	SPARC	LDSB		R[Ar+Ar/Disp]		(signed)
		LDUB		R[Ar+Ar/Disp]		(unsigned)
	------------------------------------------
	HPPA	LDB		Disp14(s,R),R
		LDBX		Ir(s,R)R
		LDBS		Disp5(s,R)R		(short)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80	LD		R[Ar+Disp]
	------------------------------------------
	IA-64	LD1.ldtype.ldhint	R1=R3     (no base update)
		LD1.ldtype.ldhint	R1=R3,R2  (base update)
		LD1.ldtype.ldhint	R1=R3,I9  (imm base update)
		      (normal load)
		    s	    (speculative load)
		    a	    (advanced load)
		    sa	    (speculative advanced load)
		   c.nc	    (check load - no clear)
		  c.clr     (check load - clear)
		c.clr.acq   (ordered check load - clear)
		   acq      (ordered load)
		   bias     (biased load)
			  .ldhint
			      (Temporary locality level 1)
			   nt1	    (No temporal locality level 1)
			   nta	    (No temporal locality all levels)
		for SIGNED: one additional operation:
			SXT1	R1=R3
		for UNSIGNED:
			ZXT1	R1=R3
	-------------------------------------------
	MCS51	MOV	8	A,addr          (A8)
				A,@Ri
				Ri,addr              	
				A,@DPTR		(A16)
	--------------------------------------------
	JVM	BALOAD	8			(Load Byte from Array)
		CALOAD  8  	                (Load Char from Array)  
	--------------------------------------------
	ARM	LDRccB	8	RM	
		LDRccBT 8       RM      	(user-mode)	
		LDRccSB 8       RM  	        (signed byte)   	
	---------------------------------------------
	SH4	MOV.B		@-R,R
				@R+,R
				@R,R
 ------------------------------------------------------------------------------
o	Load WORD (16-bit)

	x86	MOV		R[Ar+Ir+Disp]
	------------------------------------------
	Alpha	(*)	LDL/LDQ, then EXTWL/EXTWH RRR RRI
	------------------------------------------
	PPC	LHA		R[Ar]
		LHAX		R[Ar+Ir]
		LHZ		R[Ar]
		LHZX		R[Ar+Ir]
	------------------------------------------
	MIPS	LH		R[Ar+Disp]
		LHU		R[Ar+Disp]
	------------------------------------------
	SPARC	LDSH		R[Ar+Ar/Disp]		(Signed)
		LDUH		R[Ar+Ar/Disp]		(Unsigned)
	------------------------------------------
	HPPA	LDH		Disp14(s,R),R
		LDHX		Ir(s,R)R
		LDHS		Disp5(s,R)R		(short)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80	LD		R[Ar+Disp]
	------------------------------------------
	IA-64	LD2.ldtype.ldhint	R1=R3     (no base update)
		LD2.ldtype.ldhint	R1=R3,R2  (base update)
		LD2.ldtype.ldhint	R1=R3,I9  (imm base update)
		for SIGNED: one additional operation:
			SXT2	R1=R3
		for UNSIGNED:
			ZXT2	R1=R3
	------------------------------------------
	JVM	SALOAD	16			(Load Word Array)
	------------------------------------------
	ARM	LDRccH 		RM		(unsigned)
		LDRccSH         RM  	        (signed)
	---------------------------------------------
	SH4	MOV.W		@-R,R
				@R+,R
				@R,R
 ------------------------------------------------------------------------------
o	Load DWORD (32-bit)

	x86	MOV		R[Ar+Ir+Disp]
	------------------------------------------
	Alpha	LDL		R[Ar+Disp16]
	------------------------------------------
	PPC	LWZ		R[Ar]
		LWZX		R[Ar+Ir]
	------------------------------------------
	MIPS	LW		R[Ar+Disp]
		LWU		R[Ar+Disp]		
	------------------------------------------
	SPARC	LDSW		R[Ar+Ar/Disp]		(Signed) V9
		LD		R[Ar+Ar/Disp]		(Unsigned)
	------------------------------------------
	HPPA	LDW		Disp14(s,R),R		(imm. index)
		LDWX		Ir(s,R)R		(reg index)
		LDWAX		R(R)R			(absolute address)	
		LDWS		Disp5(s,R)R		(short)
		LDWAS		Disp5(s,R)R		(absolute short)
		LDWM		Disp14(s,R),R		(MODIFY BASE!!)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80	
	------------------------------------------
	IA-64	LD4.ldtype.ldhint	R1=R3     (no base update)
		LD4.ldtype.ldhint	R1=R3,R2  (base update)
		LD4.ldtype.ldhint	R1=R3,I9  (imm base update)
		for SIGNED: one additional operation:
			SXT4	R1=R3
		for UNSIGNED:
			ZXT4	R1=R3
	-------------------------------------------
	JVM	IALOAD	32			(Load Array)
		ILOAD_0	32
		ILOAD_1 32  	
		ILOAD_2 32
		ILOAD_3 32
		ILOAD	32		NUM_STACK_POS
	-------------------------------------------
	ARM	LDRcc	32	RM		
		LDRcc   32      RM              (user mode)
	---------------------------------------------
	SH4	MOV.L		@-R,R
				@R+,R
				@R,R
 ------------------------------------------------------------------------------
o	Load QWORD (64-bit)

	x86	
	------------------------------------------
	Alpha	LDQ		R[Ar+Disp16]
		LDQ_U		R[Ar+Disp16]		(Unaligned)
	------------------------------------------
	PPC	LD		R[Ar]
		LDX		R[Ar+Ir]
	------------------------------------------
	MIPS	LD		R[Ar+Disp]
	------------------------------------------
	SPARC	LDX		R[Ar+Ar/Disp]		V9
	------------------------------------------
	68K
	------------------------------------------
	z80
	------------------------------------------
	IA-64	LD8.ldtype.ldhint	R1=R3     (no base update)
		LD8.ldtype.ldhint	R1=R3,R2  (base update)
		LD8.ldtype.ldhint	R1=R3,I9  (imm base update)
	
		LD8.fill.ldhint		R1=R3
		LD8.fill.ldhint		R1=R3,R2
		LD8.fill.ldhint		R1=R3,I9
	------------------------------------------
	JVM	LALOAD	64			(Array)
		LLOAD_0	64
		LLOAD_1	64
		LLOAD_2	64
		LLOAD_3	64
		LLOAD	64		NUM_STACK_POS




  
  Store 
 

  


	Memory[EA](Size) = source


  


  


	Memory[EA](Size) = Truncate(source, Size)



 ------------------------------------------------------------------------------
o	Store BYTE (8-bit)

	x86	MOV		R[Ar+Ir+Disp]
	-----------------------------------------
	Alpha	(*) INSBL  RRR RRI, then STL/STQ, may be preload
	-----------------------------------------
	PPC	STB		R[Ar]
		STBX		R[Ar+Ir]
	------------------------------------------
	MIPS	SB		R[Ar+Disp]		
	------------------------------------------
	SPARC	STB		R[Ar+Ar/Disp]
	------------------------------------------
	HPPA	STB		R,Disp14(s,R)
		STBS		R,Disp5(s,R)		(short)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80	LD		R[Ar+Disp]
	------------------------------------------
	IA-64	ST1.sttype.sthint	[R3] = R2
		    		[R3] = R2, I9
		    rel  (ordered store)
	------------------------------------------
	MCS-51	MOV	8	addr,A          	(A8)
			 	addr,Ri
				@Ri,A	
	                        @DPTR,A			(A16)
	-------------------------------------------
	JVM	BASTORE	8       			(Array)
		CASTORE	8	                        (Array)
	-------------------------------------------
	ARM	STRccB	8	RM
		STRccBT	8				(user mode)
	---------------------------------------------
	SH4	MOV.B		R,@-R
				R,@R+
				R,@R
 ------------------------------------------------------------------------------
o	Store WORD (16-bit)

	x86	MOV		R[Ar+Ir+Disp]
	------------------------------------------
	Alpha	(*) INSWH/INSWL, then STL/STQ, may be preload
	------------------------------------------
	PPC	STH		R[Ar]
		STHX		R[Ar+Ir]
	------------------------------------------
	MIPS	SH		R[Ar+Disp]
	------------------------------------------
	SPARC	STH		R[Ar+Disp]
	------------------------------------------
	HPPA	STH		R,Disp14(s,R)
		STHS		R,Disp5(s,R)		(short)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80	LD		R[Ar+Disp]
	------------------------------------------
	IA-64	ST2.sttype.sthint	[R3] = R2
		    		[R3] = R2, I9
		    rel  (ordered store)
	------------------------------------------
	JVM	SASTORE	16				(Array)
	------------------------------------------
	ARM	STRccH	16	RM
	---------------------------------------------
	SH4	MOV.W		R,@-R
				R,@R+
				R,@R
 ------------------------------------------------------------------------------
o	Store DWORD (32-bit)

	x86	MOV		R[Ar+Ir+Disp]
	------------------------------------------
	Alpha	STL		R[Ar+Disp16]
	------------------------------------------
	PPC	STW		R[Ar]
		STWX		R[Ar+Ir]
	------------------------------------------
	MIPS	SW		R[Ar+Disp]
	------------------------------------------
	SPARC	ST		R[Ar+Ar/Disp]
	------------------------------------------
	HPPA	STW		R,Disp14(s,R)
		STWS		R,Disp5(s,R)		(short)
		STWAS		R,R(R)			(absolute short)
		STWM		R,Disp14(s,R)		(MODIFY BASE REG)
	------------------------------------------
	68K	MOVE		R[Ar+Disp]		(DA)
	------------------------------------------
	z80
	------------------------------------------
	IA-64	ST4.sttype.sthint	[R3] = R2
		    		[R3] = R2, I9
		    rel  (ordered store)
	------------------------------------------
	JVM	IASTORE	32		(Array)
		ISTORE_0
		ISTORE_1
		ISTORE_2
		ISTORE_3
		ISTORE		NUM_STACK_POS	
	------------------------------------------
	ARM	STRcc 		RM
		STRccT          RM			(user mode)
	---------------------------------------------
	SH4	MOV.L		R,@-R
				R,@R+
				R,@R
 ------------------------------------------------------------------------------
o	Load QWORD (64-bit)

	x86	
	------------------------------------------
	Alpha	STQ		R[Ar+Disp16]
		STQ_U		R[Ar+Disp16]		(Unaligned)
	------------------------------------------
	PPC	STD		R[Ar]
		STDX		R[Ar+Ir]
	------------------------------------------
	MIPS	SD		R[Ar+Disp]
	------------------------------------------
	SPARC	STX		R[Ar+Disp]		V9
	------------------------------------------
	68K
	------------------------------------------
	z80	
	------------------------------------------
	IA-64	ST8.sttype.sthint	[R3] = R2
		    		[R3] = R2, I9
		    rel  (ordered store)
	-------------------------------------------
	JVM	LASTORE	64			(Array)
		LSTORE_0
		LSTORE_1
		LSTORE_2
		LSTORE_3
		LSTORE		NUM_STACK_POS




  
  Load Unaligned 
 

  

 ------------------------------------------------------------------------------
o	Load Unaligned
	
	x86	(*) No need
	------------------------------------
	Alpha	LDQ_U	64	RM


 
  THIS SECTION IS UNDER CONSTRUCTION  
 




  
  Store unaligned 
 
  


 
  THIS SECTION IS UNDER CONSTRUCTION  
 

 ------------------------------------------------------------------------------
o	Store Unaligned


	x86	(*) No need
	------------------------------------
	Alpha	STQ_U	64	RM
	




  
  Prefetch 
 

  


	Cache[EA] = Mem[EA]	// Async



SPARC prefetch functions
	0	for several reads
	1	for one read
	2	for several writes
	3	for one write
	4	page



 ---------------------------------------------------------------------------
o	Prefetch

	x86     PREFETCH0	M
		PREFETCH1	M
		PREFETCH2	M
		PREFETCHNTA	M
	------------------------------------
	Alpha	FETCH
		FETCH_M

	------------------------------------
	PPC	DCBT
		DCBTST
	------------------------------------
	MIPS	PREF
		PREFX
	------------------------------------
	SPARC	PREFETCH -	MF	(F = function)
	------------------------------------
	HPPA	(*)	LDD ,r0
			LDW ,r0
	------------------------------------
	68K
	------------------------------------
	VAX-11
	------------------------------------
	ARM
	------------------------------------
	IA-64
	------------------------------------
	SH4




  
  Memory Barrier 
 

  


 ---------------------------------------------------------------------------
o	Memory Barrier

	x86	MFENCE
	------------------------------------
	Alpha	WMB
	------------------------------------
	PPC	MBAR
		MSYNC	
	------------------------------------
	MIPS	SYNC
	------------------------------------
	SPARC	MEMBAR
	------------------------------------
	HPPA	SYNC
	------------------------------------
	68K
	------------------------------------
	VAX-11
	------------------------------------
	ARM
	------------------------------------
	IA-64
	------------------------------------
	SH4





  
  Move between registers 
 

  


	destination = source


  


На RISC архитектурах может делаться через AND, OR итд с регистром
всегда содержащим 0.

Например SPARC:
	mov	%r5,%r6	  =>	or	%g0,%r5,%r6



 ---------------------------------------------------------------------------
o	Move between registers

	x86	MOV	8	RR
			16	RR
			32	RR
	------------------------------------
	Alpha	(*)	BIS r31, ...
	------------------------------------
	PPC	(*)	OR  rs,rs,rd
	------------------------------------
	MIPS	(*)	ADD  with r0
	------------------------------------
	SPARC   (*)	OR with r0
	------------------------------------
	HPPA	(*)	OR with r0
	------------------------------------
	68K	MOVE	RR
		MOVEA	R{A}R		To address register
	------------------------------------
	VAX-11
	------------------------------------
	IA-64	MOV	64	R1=R2		(Pop: adds R1=0,R3)
	------------------------------------------
	MCS51	MOV	8	Ri,A
				A,Ri
	------------------------------------------
	ARM	MOVcc	32	RR
	------------------------------------------
	SH4	MOV		RR

 --------------------------------------------------------------------------------
o	Load Offset

	Alpha	LDA	RRDisp16
		LDAH	RRDisp(31..16)
	------------------------------------------
	HPPA	LDO	Disp14(R),R		
	------------------------------------------
	x86	LEA




  
  Load Immediate Value 
 

  



  


	destination = immediate_cosnt





  


	destination = sign_extent(immediate_const)



Загрузка 32-битного числа в регистр на SPARC v8
	set	value,reg

		sethi	%hi(value),reg
		or	%g0, %lo(value), reg



Для SPARC v9 (64-разрядная архитектура)
	setuw	value,reg
		
		sethi 	%hi(value),reg
		or	reg,%lo(value),reg

	setsw	value,reg

		sethi	%hi(value),reg
		or	reg,%lo(value),reg
		sra	reg,%g0,reg


Для 64-разрядного значения на SPARC V9
	setx	value,reg,rd

		sethi	%uhi(value), reg
		or	reg, %ulo(value), reg
		sllx	reg,32,reg		! shift on 32 bit
		sethi	%hi(value),rd
		or	rd, reg, rd
		or	rd, %lo(value), rd



 --------------------------------------------------------------------------------
o	Load Immediate Value
	
	HPPA	LDIL	Imm21,R			(Load Immediate Low  part reg)
	------------------------------------------
	x86	MOV	8	RI	MI
			16	RI	MI
			32	RI	MI
	------------------------------------------
	IA-64	MOV	64	R1 = I22	(Pop: addl R1=I22,r0)
		MOVL	64	R1 = I64
	------------------------------------------
	MCS51	MOV	8	Ri,I8
				A,I8
	------------------------------------------
	JVM 		previously
		ICONST_M1	32
		ICONST_0
		ICONST_1
		ICONST_2
		ICONST_3
		ICONST_4
		ICONST_5
		LCONST_0        64
		LCONST_1
		BIPUSH		8	IMM8		(Push Byte)
		SIPUSH		16	IMM16		(Push Word)
		LDC1		vary	CONST_IDX8	(From Constant Pool)
		LDC2		vary	CONST_IDX16	(From Constant Pool)
		LDC2W		vary	CONST_IDX16	(LONG or DOUBLE)
	-------------------------------------------
	ARM 	(*) Complex code based on MOVcc
	-------------------------------------------
	SH4	MOV		RI



  


	destination[high_part] = immediate_const
	destination[low_part]  = source[low_part]


 -------------------------------------------------------------------------------
o	Load High Part Register

	x86	(*) No need
	------------------------------------
	Alpha	LDAH	
	------------------------------------
	PPC	ADDIS
	------------------------------------
	MIPS	LUI
	------------------------------------
	SPARC   SETHI		RI{S22}
	------------------------------------
	HPPA	LDIL
	------------------------------------
	68K	(*) No need
	------------------------------------
	VAX-11	(*) No need
	------------------------------------
	ARM
	------------------------------------
	IA-64
	------------------------------------
	SH4