35.2.1.6. СРАВНЕНИЯ И УСЛОВНЫЕ ПЕРЕХОДЫ




	            		Alpha	MIPS	HPPA	PPC	SPARC	IA-64
Return address register		any	r31	r2,r31	link	r31	



Типовой branch по флагам:


	if (Logical_Function(Flags))
	{
		Jump
	}
Логическая функция может быть просто значением
флага, или его инверсией или функцией от нескольких флагов

Пример условий и комбинаций флагов для x86:
 --------------------------------------------------------------------------
Abbr	 Unsigned Signed Condition		Description
 --------------------------------------------------------------------------
A/NBE	   >		 (CF==0) and (ZF==0)    Above/Not Below Equal
AE/NB/NC   > =		  CF==0	 		Above Equal/Not Below/Not Carry
B/NAE/C	   <		  CF==1			Below/Not Above Equal/Carry
BE/NA	   < =		 (CF==1) or  (ZF==1)	Below Equal/Not Above
E/Z	   ==     ==	  ZF==1			Equal/Zero
NE/NZ	   !=	  !=	  ZF==0			Not Equal/Not Zero
G/NLE		  >      (SF==OF) and (ZF==0) 	Greater/Not Less Equal
GE/NL		  >=     (SF==OF)		Greater Equal/Not Less
L/NGE		  <       SF!=OF		Less/Not Greater Equal
LE/NG		  <=	 (SF!=OF) or (ZF==1)	Less Equal/Not Greater
NO			  OF==0			Not Overflow
O			  OF==1			Overflow
NP/PO			  PF==0			No Parity/Parity Odd
P/PE			  PF==1			Parity/Parity even
NS			  SF==0			No Sign
S			  SF==1			Sign
 ---------------------------------------------------------------------------
Мнемоники переходов по флагам и их комбинациям
--------------------------------------------------------------------------------------
Unsigned Signed	x86	Alpha	PPC*	MIPS	SPARC	68K	HPPA	IA64	ARM
--------------------------------------------------------------------------------------
  >         	JA      ---     BGT   	---     BGU     BHI     ---    	---     BHI
		JNBE				BPGU                            
  > =           JAE     ---     BGE     ---     BCC	BCC     ---     ---     BCC
		JNB             BNL             BPCC                            BLO
		JNC
  <		JB      ---     BLT     ---     BCS     BCS     ---     ---     BCS
		JNAE                            BPCS    BLO                     BHS
		JC
  < =          	JBE     ---     BLE     ---     BLEU    BLS     ---     ---     BLS
		JNA             BNG             BPLEU
  ==      ==	JE      ---     BEQ     ---     BE      BEQ     ---     ---     BEQ
		JZ                              BPE
  !=      !=	JNE	---	BNE	---	BNE     BNE     ---     ---     BNE
		JNZ                             BPNE
          >	JG      ---     BGT     ---     BG      BGT     ---     ---     BGT
		JNLE                            BPG
          >=	JGE     ---     BGE     ---     BGE     BGE     ---     ---     BGE
		JNL             BNL             BPGE
          <	JL      ---     BLT     ---     BL      BLT     ---     ---     BLT
		JNGE                            BPL
          <= 	JLE     ---     BLE     ---     BLE     BLE     ---     ---     BLE
		JNG             BNG             BPLE
    S == 0	JNS	---	---	---	BNEG    BPL     ---     ---     BPL
						BPNEG
    S == 1      JS	---	---	---	BPOS    BMI     ---     ---     BMI
					        BPPOS
    O == 0	JNO	---	BNS	---	BVC     BVC     ---     ---     BVC
						BPVC
    O == 1	JO	---	BSO	---	BVS     BVS     ---     ---     BVS
						BPVS
    P == Even	JP 	---     --- 	---	---	---     ---     ---     ---
		JPE     
    P == Odd	JNP     ---     ---     ---     ---     ---     ---     ---     ---
		JPO  
--------------------------------------------------------------------------------------

Замечания:

PPC:    Реально есть варианты команды условного перехода:	BC,BCA,BCL,BCLA

	В CRi есть биты: LT,GT,EQ,SO.
	По каждому можно перейти если он установлен, либо снят.
	А значение зависит от того была ли предидущая операция signed
 	или unsigned.
	Например для сравнений надо использовать следущие мнемоники
		Signed compare: 	CMP, CMPI
		Unsigned compare:       CMPL, CMPLI	(Logical compare)

SPARC:	Форма  Bxx  - это обычный условный переход
	       BPxx - переход с предсказанием (branch with prediction)

68K:	Есть еще серия команд DBcc reg,label
	которые имеют теже коды условий, но используются для циклов
	таким образом изменяя значения регистра
		if (condition == false)
		{
			reg--
			if (reg != -1) Jump
		}


Branch по сравнению с нулем



	if (Specified_Compare(source, 0))
	{
		Jump
	}
Переход по сравнению регистра с 0
--------------------------------------------------------------------------------------
Unsigned Signed	x86	Alpha	PPC	MIPS	SPARC	68K	HPPA	IA64	ARM
--------------------------------------------------------------------------------------
  >         	--						(*)
  > =           --                                              (*)
  <		--                                              (*)
  < =          	--                                              (*)
  ==      ==	--	BEQ     		BRZ             (*)
  !=      !=	--      BNE                     BRNZ            (*)
          >	--      BGT             BGTZ    BRGZ            (*)
					BGTZL
					
          >=	--      BGE         	BGEZ    BRGEZ           (*)
					BGEZAL
					BGEZALL
					BGEZL
          <	--      BLT             BLTZ    BRLZ            (*)
					BLTZAL
					BLTZALL
					BLTZL
          <= 	--      BLE             BLEZ    BRLEZ           (*)
					BLEZL
--------------------------------------------------------------------------------------
Замечния:

MIPS:	L - Likely (execute delay slot only if branch is taken)
	AL - and link (i.e. it's not jump, but call)

HPPA:   Данная операция может быть сделана с помощью команды 
	Compare with Immediate and Branch (CMPIBcc), с использованием
	0 в качестве immediate операнда.
	(Смотри коды условий ниже в разделе - переход по сравнению двух
	 регистров)


Branch по сранению регистров



	if (Specified_Compare(source1, source2))
	{
		Jump
	}
Переход по сравнению двух регистров
--------------------------------------------------------------------------------------
Unsigned Signed	x86	Alpha	PPC	MIPS	SPARC	68K	HPPA	IA64	ARM
--------------------------------------------------------------------------------------
  >         	---	     		                        CMPB>>
  > =           ---                                             CMPB>>=
  <		---                                             CMPB<<
  < =          	---                                             CMPB<<=
  ==      ==	---	                BEQ                     CMPB=
					BEQL
  !=      !=	---			BNE                     CMPB<>
					BNEL
          >	---                                             CMPB>
          >=	---                                             CMPB>=
          <	---                                             CMPB<
          <= 	---                                             CMPB<=
   Overflow	---						CMPBSV
  Non Overflow	---						CMPBNSV
    Even        ---						CMPBEV
    Odd		---						CMPBOD
--------------------------------------------------------------------------------------
Замечания:

HPPA:	Реально еще есть команды типа
	CMPIB	Compare Immediate and Branch
	ADDB	Add and Branch
	ADDIB	Add Immediate and Branch


Branch по младшему биту регистра



	if (Low_Bit(source) == Desired_Value)
	{
		Jump
	}
Branch по биту регистра
--------------------------------------------------------------------------------------
		x86	Alpha	PPC	MIPS	SPARC	68K	HPPA	IA64	ARM
--------------------------------------------------------------------------------------
 ==0         	--	BLBC                                    BB>=
 ==1		--	BLBS                                    BB<
--------------------------------------------------------------------------------------
Замечания:

Alpha: только младший бит
HPPA:  любой бит регистра



TODO: Специальный случай с PowerPC Condition register PPC mtcrf mask, rS rS and mask -> CR mfcr rD CR -> rD mcrxr crfD XER[3:0] -> CRi mcrf crfD, crfS CRi -> CRj crand crD, crA, crB cror crxor crnand crnor creqv crandc crorc


Compare



	Set_Flags(source1 -  source2)
Compare on SPARC делается как
	cmp	rs,reg_imm
	
		subcc	rs,reg_imm,%g0

	! subcc - subtract and set flag,
	!	 r0 - всегда равен нулю
------------------------------------------------------------------------------ o Arithmetical Comparing x86 CMP 8 RR RI 16 RR RI 32 RR RI --------------------------------------- Alpha (*) some strange algorithm, based on: CMPEQ 32/64 RRR RRI (equal) CMPLE 32/64 RRR RRI (signed:less-equal) CMPLT 32/64 RRR RRI (signed:less) CMPULE 32/64 RRR RRI (unsigned:less-equal) CMPULT 32/64 RRR RRI (unsigned:less) --------------------------------------- PPC CMP 32 [CR]RR (Signed) 64 [CR]RR (Signed) CMPI 32 [CR]RI (Signed) 64 [CR]RI (Signed) CMPL 32 [CR]RR (Unsigned) 64 [CR]RR (Unsigned) CMPLI 32 [CR]RI (Unsigned) 64 [CR]RR (Unsigned) ---------------------------------------- MIPS (*) see Conditional Jumps ---------------------------------------- SPARC SUBCC max RRR RRI ---------------------------------------- 68K CMP 8 RR (D-regs) 16 RR 32 RR CMPA 16 RR (A-regs) 32 RR CMPI 8 RI (D-,A- regs). 16 RI 32 RI ---------------------------------------- z80 CP 8 AR AI ---------------------------------------- HPPA COMBT RR,PREL(17) (Compare, branch if true) COMBF RR,PREL(17) (Compare, branch if false) COMIBT R,Im5,PREL(17) (Compare, branch if true) COMIBF R,Im5,PREL(17) (Compare, branch if false) ADDBT RR,PREL(17) (Add, branch if true) ADDBF RR,PREL(17) (Add, branch if false) ADDIBT R,Im5,PREL(17) (Add, branch if true) ADDIBF R,Im5,PREL(17) (Add, branch if false) BVBc n,R,PREL(17) (Branch on variable bit) BBc n,RR,PREL(17) (branch on bit) ==> COMCLRc 32 RRR Compare and clear COMICLRc 32 I11,RR ------------------------------------------ IA-64 CMP.crel.ctype 64 P1,P2=R1,R2 Compare Registers (both) eq 64 P1,P2=I8,R ne unc 64 P1,P2=r0,R (signed) lt or 64 P1,P2=R,r0 le and gt or.andcm ge orcm (unsigned) ltu andcm leu and.orcm gtu geu CMP4.crel.ctype 32 P1,P2=R1,R2 Compare Lower DWORD of operds. 32 P1,P2=I8,R 32 P1,P2=r0,R 32 P1,P2=R,r0 ---------------------------------------- JVM LCMP 64 (See other in jumps) ---------------------------------------- ARM CMPcc 32 RR RI CMNcc 32 RR (compare negative) RI ---------------------------------------- SH4 CMP/EQ RR CMP/HS RR CMP/HI RR CMP/GT RR CMP/PZ RR CMP/PL RR


Logical Compare



	Set_Flags(source1 AND source2)
Logical compare на SPARC делается как:
	tst	reg1,reg2

		orcc	reg1,reg2,%g0
------------------------------------------------------------------------------- o Logical Comparing x86 TEST 8 RR RI 16 RR RI 32 RR RI ----------------------------------------- Alpha (*) complex sequence ----------------------------------------- PPC (*) complex sequence ----------------------------------------- MIPS (*) complex sequence, based on conditional Jumps ----------------------------------------- SPARC ANDCC max RRR RRI ----------------------------------------- 68K (*) complex sequence ----------------------------------------- z80 (*) complex sequence ----------------------------------------- IA-64 CMP.crel.ctype ----------------------------------------- ARM TSTcc 32 RR RI TEQcc 32 RR RI ----------------------------------------- SH4 TST RR


Jump if carry



	if (CF == 1)
	{
		Jump
	}
------------------------------------------------------------------------------- o Jump Carry (Unsigned >) x86 JC REL(8,16,32) ------------------------------------------ Alpha (*) complex sequence ------------------------------------------ PPC BC PREL(16) [CR.GT]:true ------------------------------------------ MIPS (*) ------------------------------------------ SPARC BGU PREL(?) ------------------------------------------ 68K BCS PREL(8,16,32) ------------------------------------------ z80 JR C PREL(8) JP C ADDR(16) ------------------------------------------ HPPA MOVB ?? R1,R2,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ MCS51 JC REL ------------------------------------------ SH4 (*) use BT/BF


Jump if no carry



	if (CF == 0)
	{
		Jump
	}
------------------------------------------------------------------------------- o Jump No Carry (Unsigned <=) x86 JNC REL(8,16,32) ------------------------------------------ Alpha (*) ------------------------------------------ PPC BC PREL(16) [CR.GT]:false ------------------------------------------ MIPS (*) ------------------------------------------ SPARC BLEU PREL(?) ------------------------------------------ 68K BCC PREL(8,16,32) ------------------------------------------ z80 JR NC PREL(8) JP NC ADDR(16) ------------------------------------------ HPPA MOVB ?? R1,R2,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------- MCS51 JNC REL ------------------------------------------ SH4 (*) use BT/BF


Jump if Zero



	if (ZF == 1)
	{
		Jump
	}


------------------------------------------------------------------------------- o Jump Zero (Signed/Unsigned = ) x86 JZ REL(8,16,32) ------------------------------------------ Alpha BEQ R.PREL(20) (if Reg == 0) ------------------------------------------ PPC BC PREL(16) [CRi.EQ]:true ------------------------------------------ MIPS BEQ RR.PREL(18) (if R1 = R1) ------------------------------------------ SPARC BE PREL(?) ------------------------------------------ 68K BEQ PREL(8,16,32) ------------------------------------------ z80 JR Z PREL(8) JP Z ADDR(16) ------------------------------------------ HPPA MOVB = R1,R2,PREL(17) MOVIB = R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ MCS51 JZ REL ------------------------------------------ JVM IFEQ 32 REL16 (Test Word on stack 0) IF_ICMPEQ 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF


Jump if no zero



	if (ZF == 0)
	{
		Jump
	}
------------------------------------------------------------------------------- o Jump No Zero (Signed/Unsigned !=) x86 JNZ REL(8,16,32) ------------------------------------------- Alpha BNE R.PREL(20) (if Reg != 0) ------------------------------------------- PPC BC PREL(16) [CRi.EQ]:false ------------------------------------------- MIPS BNE RR.PREL(18) (if R1 != R2) ------------------------------------------- SPARC BNE PREL(?) ------------------------------------------- 68K BNE PREL(8,16,32) ------------------------------------------ z80 JR NZ PREL(8) JP NZ ADDR(16) ------------------------------------------ HPPA MOVB <> R1,R2,PREL(17) MOVIB <> R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ MSC51 JNZ REL ------------------------------------------ JVM IFNE 32 REL16 (Test Word on stack 0) IF_ICMPNE 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF


Jump Great

------------------------------------------------------------------------------- o Jump Great (Signed >) x86 JG REL(8,16,32) ------------------------------------------- Alpha BGT R.PREL(20) (if Reg > 0) -------------------------------------------- PPC BC PREL(16) [CRi.GT]:true -------------------------------------------- MIPS BGTZ R.PREL(18) (if Reg > 0) -------------------------------------------- SPARC BG PREL(?) -------------------------------------------- 68K BGT PREL(8,16,32) -------------------------------------------- z80 (*) Complex sequence ------------------------------------------ HPPA MOVB > R1,R2,PREL(17) MOVIB > R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ JVM IFGT 32 REL16 (Test Word on stack 0) IF_ICMPGT 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF


Jump Great Equal

------------------------------------------------------------------------------- o Jump Great Equal (Signed >=) x86 JGE REL(8,16,32) ------------------------------------------- Alpha BGE R.PREL(20) (if Reg >= 0) ------------------------------------------- PPC BC PREL(16) [CRi.LT]:false ------------------------------------------- MIPS BGEZ R.PREL(18) (if Reg >= 0) ------------------------------------------- SPARC BGE PREL(?) ------------------------------------------- 68K BGE PREL(8,16,32) ------------------------------------------- z80 (*) Complex sequence ------------------------------------------ HPPA MOVB >= R1,R2,PREL(17) MOVIB >= R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ JVM IFGE 32 REL16 (Test Word on stack 0) IF_ICMPGE 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF


Jump Less Equal

------------------------------------------------------------------------------- o Jump Less Equal (Signed <=) x86 JLE REL(8,16,32) --------------------------------------- Alpha BLE R.PREL(20) (if Reg <= 0) --------------------------------------- PPC BC PREL(16) [CRi.GT]:false --------------------------------------- MIPS BLEZ R.PREL(18) (if Reg <= 0) --------------------------------------- SPARC BLE PREL(?) --------------------------------------- 68K BLE PREL(8,16,32) --------------------------------------- z80 (*) Complex sequence ------------------------------------------ HPPA MOVB <= R1,R2,PREL(17) MOVIB <= R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ JVM IFLE 32 REL16 (Test Word on stack 0) IF_ICMPLE 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF


Jump Less

------------------------------------------------------------------------------- o Jump Less (Signed <) x86 JL REL(8,16,32) ---------------------------------------- Alpha BLT R.PREL(20) (if Reg < 0) ---------------------------------------- PPC BC PREL(16) [CRi.LT]:true ---------------------------------------- MIPS BLTZ R.PREL(18) (if Reg < 0) ---------------------------------------- SPARC BL PREL(?) ---------------------------------------- 68K BLT PREL(8,16,32) ---------------------------------------- z80 (*) Complex sequence ------------------------------------------ HPPA MOVB < R1,R2,PREL(17) MOVIB < R1,Imm5,PREL(17) ------------------------------------------ IA-64 BR.XX PREL(25) R,PREL(25) ------------------------------------------ JVM IFLT 32 REL16 (Test Word on stack 0) IF_ICMPLT 32 REL16 (Compare 2 words) ------------------------------------------ SH4 (*) use BT/BF ------------------------------------------------------------------------------ Note: Else we have Jump if Overflow, and some more exotic jumps. And JUMP if = 0, <> 0 this is good jump too. And also, constructions for create loops. Add full scheme of signed/unsigned operation (JUMPS). In ARM archittecture: branchs are always conditional. So look at calls and return sections for more info.

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