35.2.1.5.





THIS SECTION IS UNDER CONSTRUCTION







	destination = sign_extent(source)
SPARC:
	signx	rd,rd
		
		sra	rs,%g0,rd




	destination = zero_extent(source)
------------------------------------------------------------------------------- o BYTE -> WORD (Signed Extend/Unsigned Extend) x86 MOVSX RR (signed) MOVZX RR (unsigned) ----------------------------------------- Alpha EXTBL RRR RRI ----------------------------------------- PPC EXTSB RR ----------------------------------------- MIPS (*) (Throught memory ????) ----------------------------------------- SPARC (*) ----------------------------------------- 68K EXT R (signed) ----------------------------------------- z80 ----------------------------------------- JVM (*) During Load only ------------------------------------------------------------------------------- o WORD -> DWORD (Signed Extend/Unsigned Extend) x86 MOVSX RR (signed) MOVZX RR (unsigned) ----------------------------------------- Alpha EXTWH RRR RRI EXTWL RRR RRI ----------------------------------------- PPC EXTSH RR (signed) ----------------------------------------- MIPS (*) (Throught memory ????) ----------------------------------------- SPARC (*) ----------------------------------------- 68K EXT R (signed) ----------------------------------------- z80 ----------------------------------------- JVM (*) During Load only ------------------------------------------------------------------------------- o DWORD -> QWORD (Signed Extend/Unsigned Extend) x86 (*) ------------------------------------------ Alpha EXTLL RRR RRI EXTLH RRR RRI ------------------------------------------ PPC (*) ------------------------------------------ MIPS (*) ----------------------------------------- SPARC (*) ----------------------------------------- 68K (*) ----------------------------------------- z80 ----------------------------------------- JVM I2L (dword -> qword) L2I (qword -> dword) ------------------------------------------------------------------------------- o BYTE -> DWORD (Signed Extend/ Unsigned Extend) x86 MOVSX RR MOVZX RR ------------------------------------------- Alpha EXTBL RRR RRI ------------------------------------------- PPC EXTSB RR ------------------------------------------- MIPS (*) Throught memory ???? ------------------------------------------- SPARC (*) ------------------------------------------- 68K (*) complex sequence ------------------------------------------- z80 (*) complex sequence ------------------------------------------- JVM (*) During Load only ------------------------------------------------------------------------------ Note: HPPA architecture use: VEXTRU/VEXTRS/EXTRU/EXTRS (for extract) VDEP/DEP/VDEPI/DEPI/ZVDEP/ZDEP/ZVDEPI (for deposit) This instruction fetches/extract variables as bit string with/without sign extension. Good for Type conversion. But in RISC cpu's usually type conversion proceed only then store var in memory Note: Need also Big-Little Endian Conversion operations Note: To Lower-size conversions (JVM) INT2BYTE INT2CHAR INT2SHORT

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