Vector Data Formats:
	[ BYTE x  8  ]	= 64bit
	[ WORD x  4  ]	= 64bit
	[ DWORD x 2  ]	= 64bit

PACK2/PACK4		- Pack
PADD1/PADD2/PADD4	- Parallel Add
PAVG1/PAVG2		- Parallel Average
PAVGSUB1/PAVGSUB2	- Parallel Average Subtract
PCMP1/PCMP2/PCMP4	- Parallel Compare
PMAX1/PMAX2		- Parallel Maximum
PMIN1/PMIN2		- Parallel Minimum
PMPY2			- Parallel Multiply
PMPYSHR2		- Parallel Multiply and Shift Right
POPCNT			- Population Count
PSAD1			- Parallel Sum of Absolute Differences
PSHL2/PSHL4		- Parallel Shift Left
PSHLADD2		- Parallel Shift Left and Add
PSHR2/PSHR4		- Parallel Shift Right
PSHRADD2		- Parallel Shift Right and add
PSUB1/PSUB2/PSUB4	- Parallel Subtract

| Alpha	    |
look like since 21264 only (MVI)

Vector Data Formats:
 	[ BYTE x 8 ]	= 64 bit
	[ WORD x 4 ]	= 64 bit

(Not vector, but join with multimedia)				Extension
CTLZ			- Counting Leading Zeroes		CIX
CTPOP			- Count Population			CIX
CTTZ			- Count Trailing Zeroes			CIX
SEXTB			- Sign Extend Byte			BWX
SEXTW			- Sign Extend Word			BWX
			(BWX extension also support unsigned byte load/store)

MINUB8			- Vector Unsigned Byte Minimum		MVI
MINSB8			- Vector Signed Byte Minimum		MVI
MINUW4			- Vector Unsigned Word Minimum		MVI
MINSW4			- Vector Signed Word Minimum		MVI
MAXUB8			- Vector Unsigned Byte Maximum		MVI
MAXSB8			- Vector Signed Byte Maximum		MVI
MAXUW4			- Vector Unsigned Word Maximum		MVI
MAXSW4			- Vector Signed Word Maximum		MVI
PERR			- Pixel Error				MVI
PKLB			- Pack Longwords to Bytes		MVI
PKWB			- Pack Words to Bytes			MVI
UNPKBL			- Unpack bytes to Longwords		MVI
UNPKBW			- Unpack Bytes to Words			MVI

|    x86      |	

Main set of Vector Instruction on x86 is MMX (Multimedia Extensions Set).

MMX Instruction Set [Pentium w/MMX, Pentium II]

	MM Registers (64-bit)

Vector Data Formats:
	[ BYTE  x 8 ]	= 64bit
	[ WORD  x 4 ]	= 64bit
	[ DWORD x 2 ]	= 64bit
	[ QWORD	    ]	= 64bit		(Logic and Shifts only)

MOVQ			- Move 64-bit
PACKSSWB/PACKSSDW	- Pack with Signed Saturation
PACKUSWB		- Pack with Unsigned Saturation
PADDSB/PADDSW		- Packed Add with Saturation
PADDUSB/PADDUSW		- Packed Add Unsigned with Saturation
PAND			- Bitwise Logical And
PANDN			- Bitwise Logical And-Not
PCMPEQB/PCMPEQW/PCMPEQD - Packed Compare for Equal
PCMPGTB/PCMPGTW/PCMPGTD	- Packed Compare for Greater Than
PMADDWD			- Packed Multiply and Add
PMULHW			- Packed Multiply High
PMULLW			- Packed Multiply Low
POR			- Bitwise Logical Or
PSLLW/PSLLD/PSLLQ	- Packed Shift Left Logical
PSRAW/PSRAD		- Packed Shift Right Arithmetic
PSRLW/PSRLD/PSRLQ	- Packed Shift Right Logical
PSUBB/PSUBW/PSUBD	- Packed Subtract
PSUBSB/PSUBSW		- Packed Subtract with Saturation
PSUBUSB/PSUBUSW		- Packed Subtract Unsigned with Saturation
PUNPCKHBW/PUNPCKHWD/	- Unpack High Packed Data
PUNPCKLBW/PUNPCKLWD/	- Unpack Low Packed Data
PXOR			- Bitwise Logical Exclusive OR
(below is KNI SIMD instuctions, which is add-on to MMX) 
PAVGB/PAVGW		- Packed Average
PEXTRW			- Extract Word
PINSRW			- Insert Word
PMAXSW			- Packed Signed Integer Word Maximum
PMAXUB			- Packed Unsigned Integer Byte Maximum
PMINSW			- Packed Signed Integer Word Minimum
PMINUB			- Packed Unsigned Integer Byte Minimum
PMOVMSKB		- Move Byte Mask To Integer (Mask is sign bits of ops)
PSADBW			- Packed Sum of Absolute Differences
PSHUFW			- Packed Shuffle Word

SIMD2 extensions to MM register operations
PADDQ			- Add 
PSUBQ			- Sub

Williamette SIMD2 Extensions [Pentium 4]:

	XMM Registers (128-bit)

	[ BYTE  x 16 ]	= 128 bit
	[ WORD  x 8  ]	= 128 bit
	[ DWORD x 4  ]  = 128 bit
	[ QWORD x 2  ]	= 128 bit

PADDSW/PADDSW			- Add with Saturation
PADDUSB/PADDUSW			- Add with Saturation (Unsigned)
PSUBSB/PSUBSW			- Sub with Saturation
PSUBUSB/PSUBUSW			- Sub with Saturation (Unsigned)

PMULHW/PMULHUW			- Multiply High (W)
PMULLW				- Multiply Low (W)
PMULUDQ				- Multiply Unsigned (DQ)


PANDN				- And Not
PAND				- And
POR				- Or
PXOR				- Xor

PAVGV/PAVGW			- Average
PCMP(EQ/GT)B/W/D		- Compare

PSADBW				- Sum of Absolute Differences
PMADDWD				- Multiply-Add

MOVDQA				- Move aligned
MOVDQU				- Move unalifned
MOVDQ2Q				- XMM => MM
MOVQ2DQ				- MM  => XMM

| MIPS    |

MDMX - MIPS  Digital Media Extension

	[ 8 x U_BYTE  ]	= 64 bit	OB (Oct Bytes Format)
	[ 4 x U_WORD  ]	= 64 bit	QH (Quad Half Format)

MDMX shared 32 64-bit registers with FPU.

Use existing FPU operations for load vectors and it's parts
	LDC1/LDXC1/LUXC1 - for load
	SDC1/SDXC1/SUXC1 - for store 

All instructions have postfixes .OB or .QH:

MSGN				-
C.EQ/C.LT/C.LE			- Compare and Branch?
MIN/MAX				- Minimum/Maximum	
ADD/SUB				- Add/Subtract
ADD{A,L}/SUB{A,L}		-
AND/XOR/OR/NOR			- Logical Operations 
MUL/MULS{,L}/MUL{A,L}		- Multtiply
SLL/SRL/SRA			- Shifts
ANLI.OB/ANLV.OB			- Align Vector OB format
ANLI.QH/ANLV.QH			- Align Vector QH format
SHFL				- Shuffle
WAC/RAC				-

Detailed for .OB:
ADD.OB		- Vector Add	
ALNI.OB		- Vector Align, Constant ..
C.EQ.OB		- Vector Compare
MAX.OB		- Vector Maximum
MIN.OB		- Vector Minimum
MULA.OB		- Vector Multiply Accumulate
MULL.OB		- Vector Multiply and Load accumulator
MULS.OB		- Vector Multiply and Subtract Accumulator
MULSL.OB	- Vector Multiply, Subtract and Load accumulator
PICKF.OB	- Vector Pick False
PICKT.OB	- Vector Pick True
RACH.OB		- Vector Read Acc High
RACL.OB		- Vector Read Acc Low
RACM.OB		- Vector Read ACC Middle
RZU.OB		- Vector Scale, Round and Clamp Acc
SHFL.PACH.OB	- Shuffle
SLL.OB		- Vector Logical Shift Left
WACH.OB		- Vector Write Acc High
WACL.OB		- Vector Write Acc Low

| Power PC  |

PowerPC G4 AntiVect ISA extension:

Vector Data Format:

	V-registers (128 bit)

	[ 16 x SIGNED BYTE	 ] = 128 bit
	[ 16 x UNSIGNED BYTE	 ] = 128 bit
	[ 8  x SIGNED HALFWORD   ] = 128 bit
	[ 8  x UNSIGNED HALFWORD ] = 128 bit
	[ 4  x SIGNED WORD       ] = 128 bit
	[ 4  x UNSIGNED WORD	 ] = 128 bit

LVEBX   - Load Vector Element Byte Indexed
LVEHW	- Load Vector Element Half Word Indexed
LVEWX	- Load Vector Element Word Indexed
LVSL	- Load Vector for shift left
LVSR	- Load Vector for shift rigth
LVX	- Load Vector Indexed
LVXL	- Load Vector Indexed LRU
(MFVSCR) - Move from Vector Status and Control Register
(MTVSCR) - Move to Vector Status and Control Register
STVEBX	 - Store Vector Element Byte Indexed
STVEHX	 - Store Vector Element Half Word Indexed
STVEWX	 - Store Vector Element Word Indexed
STVX	 - Store Vector Indexed
STVXL	 - Store Vector Indexed LRU
VADDCUW	 - Vector Add Carryout Unsigned Word
VADDSBS	 - Vector Add Signed Byte Saturate
VADDSHS	 - Vector Add Signed Half Word Saturate
VADDSWS  - Vector Add Signed Word Saturate
VADDUBM	 - Vector Add Unsigned Byte Modulo
VADDUBS	 - Vector Add Unsigned Byte Saturate
VADDUHM	 - Vector Add Unsigned Half Word Modulo
VADDUHS	 - Vector Add Unsigned Half Word Saturate
VADDUWM	 - Vector Add Unsigned word modulo
VADDUWS	 - Vector Add Unsigned Word Saturate
VAND	 - Vector Logical AND
VANDC	 - Vector Logical AND with Complement
VAVGSB	 - Vector Avarage Signed Byte
VAVGSH	 		  Signed Half Word	
VAVGSW			  Signed Word	
VAVGUB			  Unsigned Byte
VAVGUH			  Unsigned Half Word 
VAVGUW			  Unsigned Word
VCMPEQUB/VCMPEQUB. - Vector Compare Equal-to Unsigned Byte
VCMPEQUH/VCMPEQUH.	                     Unsigned Half Word
VCMPEQUW/VCMPEQUW.			     Unsigned Word	
VCMPGTSB/VCMPGTSB. - Vector Compare Greater to Signed Byte
VCMPGTSH/VCMPGTSH.			       Signed Half Word				       	
VCMPGTSW/VCMPGTSW.			       Signed Word
VCMPGTUB/VCMPGTUB.			       Unsigned Byte
VCMPGTUH/VCMPGTUH.			       Unsigned Half Word	
VCMPGTUW/VCMPGTUW.			       Unsigned Word
VMAXSB			Vector Maximum	Signed Byte
VMAXSH				Signed Half Word
VMAXSW				Signed Word
VMAXUB				Unsigned Byte
VMAXUH				Unsigned Half Word
VMAXUW				Unsigned Word
VMHADDSHS	Vector Multiply High and Add Signed Half Word Saturate
VMHRADDSHS	Vector Multiply High Round and Add Signed Half Word Saturate
VMINSB		Vector Minimum	Signed Byte
VMINSH				Signed Half Word
VMINSW				Signed Word
VMINUB				Unsigned Byte
VMINUH				Unsigned Half Word
VMINUW				Unsigned Word
VMLADDUHM	Vector Multiply Low and Add Unsigned Half Word Modulo
VMRGHB		Vector Merge High Byte
VMRGHH		Vector Merge High Half Word
VMRGHW		Vector Merge High Word
VMRGLB		Vector Merge Low Byte
VMRGLH		Vector Merge Low Half Word
VMRGLW		Vector Merge Low Word
VMSUMMBM	Vector Multiply Sum Mixed-Sign Byte Modulo
VMSUMSHM	Vector Multiply Sum Signed Half Word Modulo
VMSUMSHS	Vector Multiply Sum Signed Half Word Saturate
VMSUMUBM	Vector Multiply Sum Unsigned Byte Modulo
VMSUMUHM	Vector Multiply Sum Unsigned Half Word Modulo
VMSUMUHS	Vector Multiply Sun Unsigned Half Word Saturate
VMULESB		Vector Multiply Even Signed Byte
VMULESH				     Signed Half Word	
VMULEUB				     Unsigned Byte	
VMULEUH				     Unsigned Half Word
VMULOSB		Vector Multiply Odd Signed Byte
VMULOSH				    Signed Half Word 	
VMULOUB				    Unsigned Byte	
VMULOUH				    Unsigned Half Word
VNOR		Vector Logical NOR
VOR		Vector Logical OR
VPERM		Vector Permute
VPKPX		Vector Pack Pixel32
VPKSHSS		Vector Pack Signed Half Word Signed Saturate
VPKSHUS		Vector Pack Signed Half Word Unsigned Satuate
VPKSWSS		Vector Pack Signed Word Signed Saturate
VPKSWUS		Vector Pack Signed Word Unsigned Saturate
VPKUHUM		Vector Pack Unsigned Half Word Unsigned Modulo
VPKUHUS		Vector Pack Unsigned Half Word Unsigned Saturate
VPKUWUM		Vector Pack Unsigned Word Unsigned Modulo
VPKUWUS		Vector Pack Unsigned Word Unsigned Saturate
VRLB		Vector Rotate Left Integer Byte
VRLH					   Half Word
VRLW					   Word
VSEL		Vector Conditional Select
VSL		Vector Shift Left
VSLB		Vector Shift Left Integer Byte
VSLDOI		Vector Shift Left Double by Octet Immediate
VSLH		Vector Shift Left Integer Half Word
VSLO		Vector Shift Left by Octet
VSLW		Vector Shift Left Integer Word
VSPLTB		Vector Splat Byte (i.e. write byte to all vector)
VSPLTH			     Half Word
VSPLTW			     Word
VSPLTISB	Vector Splat Immediate Signed Byte
VSPLTISH			       Signed Half Word		
VSPLTISW			       Signed Word
VSR		Vector Shift Right
VSRAB		Vector Shift Right Alrebraic Byte
VSRAH					     Half Word
VSRAW					     Word
VSRB		Vector Shift Right Byte
VSRH				   Half Word
VSRW				   Word
VSRO		Vector Shift Right by Octet
VSUBCUW		Vector Subtracted Carryout Unsigned Word
VSUBSBS		Vector Subtract Signed Byte Saturate
VSUBSHS				Signed Half Word Saturate
VSUBSWS				Signed Word Saturate
VSUBUBM		Vector Subtract Unsigned Byte Modulo
VSUBUBS		Vector Subtract Unsigned Byte Saturate
VSUBUHM				Unsigned Half Word Modulo
VSUBUHS				Unsigned Half Word Saturate
VSUBUWM				Unsigned Word Modulo
VSUBUWS				Unsigned Word Saturate
VSUMSWS		Vector Sum Across Signed Word Saturate
VSUM2SWS	Vector Sum Across Partial (1/2) Signed Word Saturate
VSUM4SBS	Vector Sum Across Partial (1/4) Signed Byte Saturate
VSUM4SHS	Vector Sum Across Partial (1/4) Unsigned Half Word Saturate
VSUM4UBS	Vector Sum Across Partial (1/4) Unsigned Byte Saturate
VUPKHPX		Vector Unpack High Pixel16
VUPKHSB		Vector Unpack High Signed Byte
VUPKHSH		Vector Unpack High Signed Half Word
VUPKLPX		Vector Unpack Low Pixel16
VUPKLSB		Vector Unpack Low Signed Byte
VUPKLSH		Vector Unpack Low Signed Half Word
VXOR		Vector Logical XOR

| HP-PA 2  |

HADD		Halfword parallel add (modular)
HADD,SS		Halfword parallel add (signed saturation)
HADD,US		Halfword parallel add (unsigned saturation)
HAVG		Halfword parallel Average
HSHL		Halfword Parallel shift left
HSHLADD		Halfword Parallel shift left and add
HSHR		Halfword Parallel Shift right (signed)
HSHR,U		Halfword Parallel shift right (unsigned)
HSHRADD		Halfword parallel shift right and add
HSUB		Halfword parallel subtract
HSUB,SS		Halfword parallel subtract (signed saturation)
HSUB,US		Halfword parallel subtract (unsigned saturation)

MIXH,L		Mix Halfwords left
MIXH,R		Mix Halfwords right
MIXW,L		Mix Words Left
MIXW,R		Mix Words right

PERMH		Permute Halfwords

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