35.3.4.2. INTEGER LOAD/STORE ON ALPHA




Alpha Memory Format
+-----------------------+		
| 31..26	Opcode	|
| 25..21	Ra	|
| 20..16	Rb	|
| 15..0		mdisp	|
+-----------------------+


Load	Address
	LDA	Ra.wq,disp.ab(Rb.ab)	!Memory Frmat
	LDAH	Ra.wq,disp.ab(Rb.ab)	!Memory Frmat

	Ra <- Rbv + SEXT(disp)		!LDA
	Ra <- Rbv + SEXT(disp << 16)	!LDAH

	LDA	08
	LDAH	09



Load Memory Data into Integer Register

	LDL	Ra.wq,disp.ab(Rb.ab)	!Memory Format
	LDQ	Ra.wq,disp.ab(Rb.ab)	!Memory Format


	va <- { Rbv + SEXT(disp) }
	Ra <- SEXT((va)<31:0>)		! LDL
	Ra <- (va)<63:0>		! LDQ

	LDL	28
	LDQ	29


Load Unaligned Memory Data into Integer Register

	LDQ_U	Ra.wq,disp.ab(Rb.ab)	!Memory Format

	va <- {{Rbv + SEXT(disp)} AND NOT 7 }
	Ra <- (va)<63:0>

	LDQ_U	0B



Store Integer Register Data into Memory
	
	STL	Ra.rq,disp.ab(Rb.ab)	!Memory Format

	va <- { Rbv + SEXT(disp) }
	(va)<31:0> <- Rav<31:0>		!STL
	(va)	   <- Rav		!STQ

	STL	2C
	STQ	2D


Store Unaligned Integer Register Data into Memory

	STQ_U	Ra.rq,disp.ab(Rb.ab)	!Memory Format

	
	va <- {{Rbv + SEXT(disp)} AND NOT 7 }
	(va)<63:0> <- Rav

	STQ_U	0F



Load Memory Data into Register Locked

	LDL_L	Ra.wq,disp.ab(Rb.ab)	!Memory Format
	LDQ_L	Ra.wq,disp.ab(Rb.ab)	!Memory Format

	va <- { Rbv + SEXT(disp) }
	lock_flag <- 1
	locked_physical_address <- PHYSICAL_ADDRESS(va)
	Ra <- SEXT(va)<31:0>			! LDL_L
	Ra <- va<63:0>				! LDQ_L


	LDL_L	2A
	LDQ_L	2B


Store Integer Registers Data into Memory Conditional

	STL_C	Ra.mq,disp.ab(Rb.ab)	!Memory format
	STQ_C	Ra.mq,disp.ab(Rb.ab)	!Memory format

	va <- { Rbv + SEXT(disp) }
	if lock_flag EQ 1 THEN
		(va)<31:0> <- Rav<31:0>		! STL_C
		(va) <- Rav			! STQ_C
	Ra <- lock_flag
	lock_flag <- 0

	STL_C	2E
	STQ_C	2F


Note:
	For load data values low that dword, need to use next
commands:

EXTBL/EXTWL/EXTLL/EXTQL		Extract xxx low
EXTWH/EXTLH/EXTQH		Extract xxx high

	For store data values which low that word need to use
next commands

INSBL/INSWL/INSLL/INSQL		Insert  xxx low
INSWH/INSLH/INSQH		Insert  xxx high

ZAP				Zero bytes


On Extended Alpha Architecture possible usage of
	
SEXTB/SEXTW			Sign Extend
LDBU/LDWU			Load Unsignef byte/word


For more info refer to type conversion section.


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