5.6.





library ieee; use ieee.std_logic_1164.all; entity FRONT_RISE is port( I : in std_logic; O : out std_logic); end FRONT_RISE; architecture Example of FRONT_RISE is signal NI:std_logic; -- Data after inverter begin process(I) begin NI <= not I after 5 ns; end process; O <= I and NI after 1 ns; end Example; :




library ieee; use ieee.std_logic_1164.all; entity FRONT_FALL is port( I : in std_logic; O : out std_logic); end FRONT_FALL; architecture Example of FRONT_FALL is signal NI:std_logic; -- Data after inverter begin process(I) begin NI <= not I after 5 ns; end process; O <= I nor NI after 1 ns; end Example; :




library ieee; use ieee.std_logic_1164.all; entity FRONT_BOTH is port( I : in std_logic; O : out std_logic); end FRONT_BOTH; architecture Example of FRONT_BOTH is signal NI:std_logic; -- Data after 1st inverter signal NI2:std_logic; -- Data after 2nd inverter begin process(I) begin NI <= not I after 5 ns; end process; process(NI) begin NI2 <= not NI after 5 ns; end process; O <= I xor NI2 after 1 ns; end Example;


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