11.8. СУММАТОР НЕИЗВЕСТНОГО РАЗМЕРА НА HDL

  
  Описание Generic сумматора VHDL 
 

	library ieee;
	use ieee.std_logic_1164.all;

	entity add_N is
		generic(N: positive);
		port( 
			A: in std_logic_vector((N-1) downto 0);
			B: in std_logic_vector((N-1) downto 0);
			X: out std_logic_vector((N-1) downto 0);
			C: out std_logic
		);
	end add_N;

	architecture Example of add_N is

		component SUM1 
			port(
	    			A0, B0, P0 : in std_logic;
	    			P1,  S1 : out std_logic);
		end component;


		signal	IC: std_logic_vector(N downto 0);
        begin
		IC(0) <= '0';

		stages : for i in 0 to (N-1) generate
        		add: SUM1
				port map( A0 => A(i),
				  B0 => B(i),
				  S1 => X(i),	
				  P0 => IC(i),
				  P1 => IC(i+1));
		end generate stages;
		C <= IC(N);
	end Example;	



  
  Конкретизация Generic сумматора на VHDL 
 

	library ieee;
	use ieee.std_logic_1164.all;

	entity add6 is
		port( 
			A6: in std_logic_vector(5 downto 0);
			B6: in std_logic_vector(5 downto 0);
			X6: out std_logic_vector(5 downto 0);
			C6: out std_logic
		);
	end add6;

	architecture Example of add6 is

		component add_N is
			generic(N: positive);
			port( 
				A: in std_logic_vector((N-1) downto 0);
				B: in std_logic_vector((N-1) downto 0);
				X: out std_logic_vector((N-1) downto 0);
				C: out std_logic);
		end component;
	begin
        	U6:  add_N
	 		generic map (N => 6)
	 		port map(
	        		A => A6,
	    			B => B6,
	    			X => X6,
	    			C => C6);
	end Example;


Результат синтеза:
  

Имплементация в Xilinx VIRTEX-E:
  




  
  Описание Generic сумматора Verilog 
 

	module adder(cout,sum,a,b,cin);
	parameter Size = 8;
	output	cout;
	output [Size-1:0] sum;
	input	cin;
	input [Size-1:0] a,b;
	assign {cout,sum} = a + b + cin;
	endmodule;



  
  Конкретизация Generic сумматора на Verilog 
 

	adder #(16) adder_16(cout_A,
			     sum_A,
			     a_A,
			     b_A,
			     cin_A);