35.2.1.4.2. СЕМАФОРНЫЕ ОПЕРАЦИИ

  
  Semaphore Operations 
 


Типовые опрерации для CISC машин:

Exchange:
  


	temp = source
	Start Bus Lock
	[
		source = Memory[EA]
		Memory[EA] = temp
	]
	Finish Bus Lock




Exchange and Add:
  


	Start Bus Lock
	[
		temp = Memory[EA]
		Memory[EA] = temp + source
	]
	Finish Bus Lock
	destination = temp




Compare and Exchange
  


	Start Bus Lock
	[
		temp = Memory[EA]
		if (temp == comparand)
		{
			Memory[EA] = source
		}
	]
	destination = temp




Типовые операции для RISC машин:

  

	lock_flag = 1
	lock_address = EA
	destination = Memory[EA]




  

	Each bus cycle
	[
		if (Bus.Address == EA)
		{
			lock_flag = 0;
		}
	]	



  

	if (lock_flag == 1)
	{
		Memory[EA] = source
	}
	destination = lock_flag
	lock_flag = 0	





Alpha:
        LDL_L	Reg, Mem	! 4-bytes
	LDQ_L	Reg, Mem	! 8-bytes

	Reg = Memory[EA];
	lock_flag = 1;
	locked_physical_address = EA



	STL_C	Reg, Mem	! 4-bytes
	STQ_C	Reg, Mem	! 8-bytes

	if (lock_flag == 1)
	{
		Memory[EA] = Reg
	}
	Reg = lock_flag
	lock_flag = 0;






Как правило для RISC процессоров адресс семафора должен быть выровнен на
соответсвующую границу памяти (и либо не должно быть других обращений памяти
внутри синхронизациионной секции, либо они должны быть к той же странице,
или более того в пределах например 16 байт от семафора.


Пример реализации обычных примитивов для PowerPC:

# Atomic Fetch
#		r3	- address
#		r4	- data

	loop:	lwarx	r4,0,r3		# load
		stwcx.	r4,0,r3		# store old value if still reserved
		bne-	loop


# Fetch and Store (Exchange)
#               r3	- address
#		r4	- new value
#		r3	- old value

	loop:	lwarx	r5,0,r3		# load
		stwcx.	r4,0,r3		# store if still reserved
		bne-	loop


# Fetch and Add 
#		r3	- address
#		r4	- value to add
#		r5	- old value

	loop:	lwarx	r5,0,r3 	# read
		add	r0,r4,r5	# modify
		stwcx.	r0,0,r3		# write
		bne-	loop


# Fetch and And 
#		r3	- address
#		r4	- value to and
#		r5	- old value

	loop:	lwarx	r5,0,r3 	# read
		and	r0,r4,r5	# modify
		stwcx.	r0,0,r3		# write
		bne-	loop


# Test and Set
#		r3	- address
#		r4	- new value (!=0)
#		r5	- old value

	loop:	lwarx	r5,0,r3
		cmpwi	r5,0
		bne-	$+12
		stwcx.	r4,0,r3
		bne-	loop


# Compare and Swap
#		r3	- address
#		r4	- comparant / old value
#		r5	- new value

	loop:	lwarx	r6,0,r3
		cmpw	r4,r6
		bne-	exit
		stwcx.	r5,0,r3
		bne-	loop
	exit:	mr	r4,r6









 ------------------------------------------------------------------------------
o	Semaphores Support tools

	x86	XCHG	8	RM
			16	RM
			32	RM
	------------------------------------------
	Alpha	LDL_L	32	R[Ar+Disp16]
		STL_C	32	R[Ar+Disp16]
		LDQ_L	64	R[Ar+Disp16]
		STQ_L	64	R[Ar+Disp16]
	------------------------------------------
	PPC	LWARX
		STWCX
	------------------------------------------
	MIPS	LL	32	R[Ar+Disp16]
		SC	32	R[Ar+Disp16]
		LLD	64	R[Ar+Disp16]
		SCD	64	R[Ar+Disp16]
	------------------------------------------
	SPARC	(*) Need to seek
		CASA
		CASX
	------------------------------------------
	HPPA	LDCWX	32	Disp14(s,R)R		(Load & Clear)
		LDCWS	32	Disp5(s,R)R		(Load & Clear short)
	
	------------------------------------------
	68K	TAS	8	?			(EA) (Test and Set)
		TST	8	?			(EA) (Test)
			16	?
			32	?
		CAS	RRM				(CMPXCHG   analog)
		CAS2	RRM				(CMPXCHG8B analog)
	------------------------------------------
	z80	(None tools for support semaphores)
	------------------------------------------
	IA-64	CMPXCHG1	8	R1 = [R3],R2,ar.ccv	(~CMPXCHG)
		CMPXCHG2       16	R1 = [R3],R2,ar.ccv
		CMPXCHG4       32	R1 = [R3],R2,ar.ccv	
		CMPXCHG8       64	R1 = [R3],R2,ar.ccv	
		
		FETCHADD4.sem.ldhint	R1 = [R3],inc(3)		(~XADD)
		FETCHADD8.sem.ldhint	R1 = [R3],inc(3)
			  acq
			  rel
		XCHG1.ldhint		R1 = [R3],R2		(~XCHG)
		XCHG2.ldhint		R1 = [R3],R2
		XCHG3.ldhint		R1 = [R3],R2
		XCHG4.ldhint		R1 = [R3],R2
	--------------------------------------------
	MCS51	XCH	8	A,addr		(A8)
				A,@Ri
 -------------------------------------------------------------------------------
Note:	LMW/STMW (PPC)  - Load Multiple Words/Store Multiple Words.
	STBYS	 (HPPA) - Store bytes shorts

	MCS-51 architecture - lot of memory,memory loads/store

	Signed and Unsigned Loading.
	Immediate Data Loading.
	Add Here all Load/Store & Modify Base Register